1. Field of the Invention
This invention relates generally to computer memory and, more particularly, to system and method for writing data to a cache on a cache miss.
2. Description of the Related Art
A cache is a small, fast memory holding recently accessed data that is designed to speed up subsequent processor-memory access to the same data. When data is written to or read from a main memory, a copy of the data is also saved in the cache, along with the associated main memory address. The cache monitors addresses of subsequent reads and writes to see if the requested data is already in the cache. If the requested data is stored in the cache (a cache hit), then the requested data is returned immediately and the main memory read is aborted. If the requested data is not stored in the cache (a cache miss), then the requested data is fetched from main memory and saved in the cache.
If there is a cache miss during a write, the cache puts all writes into the appropriate cache line whenever a write is done based on the general assumption that the written data is likely to be read back again at some point in the near future. In other words, the cache will always retrieve the data from the main memory on a cache miss even on a write operation where the data from the main memory is not needed. Thus, retrieving the data from the main memory during a cache miss means that on a write cache miss, the cache controller must always update the cache. Updating the cache after fetching data from main memory increases latency, and takes up memory bandwidth and power.
In view of the foregoing, there is a need to provide system and method for reducing latency, and reducing memory power and bandwidth consumption on a write operation missing the cache.